The present invention is directed generally to data communication. More particularly, the present invention relates to methods and arrangements for transferring data over parallel data circuits and to encoding and decoding schemes for achieving relatively error-free data transfers between nodes.
The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. These complex circuits are often designed as functionally-defined modules that operate on a set of data and then pass that data on for further processing. This communication from such functionally-defined modules can be passed in small or large amounts of data between individual discrete circuits, between integrated circuits within the same chip, and between remotely-located circuits coupled to or within various parts of a system or subsystem. Regardless of the configuration, the communication typically requires closely-controlled interfaces to insure that data integrity is maintained and that circuit designs are sensitive to practicable limitations in terms of implementation space and available operating power.
The demand for high-powered, high-functioning semiconductor devices has lead to an ever-increasing demand for accelerating the speed at which data is passed between the circuit blocks. Many of these high-speed communication applications can be implemented using parallel data transmission in which multiple data bits are simultaneously sent across parallel communication paths. Such xe2x80x9cparallel bussingxe2x80x9d is a well-accepted approach for achieving data transfers at high data rates. For a given data-transmission rate (sometimes established by a clock passed along with the data), the bandwidth, measured in bits-per-second, is equivalent to the data transmission rate times the number of data signals comprising the parallel data interconnect.
A typical system might include a number of modules that interface to and communicate over a parallel data communication line (sometimes referred to as a data channel); for example, in the form of a cable, a backplane circuit, a bus structure internal to a chip, other interconnect, or any combination of such communication media. A sending module would transmit data over the bus synchronously with a clock on the sending module. In this manner, the transitions over the parallel signal lines leave the sending module in a synchronous relationship with each other and/or to the clock on the sending module. At the other end of the parallel data interconnect, the data is received along with a clock signal; the receive clock is typically derived from or is synchronous with the clock on the sending module. The rate at which the data is passed over the parallel signal lines is sometimes referred to as the (parallel) xe2x80x9cbus rate.xe2x80x9d
In such systems, it is beneficial to ensure that the received signals (and where applicable, the receive clock) have a specific phase relationship to the transmit clock, to provide proper data recovery. There is often an anticipated amount of time xe2x80x9cskewxe2x80x9d between the transmitted data signals themselves and between the data signals and the receive clock at the destination. There are many sources of skew including, for example, transmission delays introduced by the capacitive and inductive loading of the signal lines of the parallel interconnect, variations in the I/O (input/output) driver source, intersymbol interference and variations in the transmission lines"" impedance and length. Regardless of which phenomena cause the skew, achieving communication with proper data recovery, for many applications, should take this issue into account.
For parallel interconnects serving higher-speed applications, in connection herewith it has been discovered that skew is xe2x80x9cpattern dependentxe2x80x9d and that the severity of this issue can be mitigated and, in many instances, largely overcome. This pattern dependency results in part from the imperfect current sources shared between the data bits in the parallel bus. The shared current sources induce skew at the driver, which directly reduces margin at the receiver, which in turn can cause data transmission errors.
More particularly, it has been discovered that when the digital data set, being sent over a high-speed parallel communication line, suddenly changes between a set of logical zeroes and a set of logical ones, the received signals are delayed due to the effect of the impedance levels (resistive, inductive and/or capacitive) in the lines feeding the internal Vdd and Vss pads. The internal Vdd and Vss pads provide the power that is shared by the respective data-transmitting output drivers. Consider, for example, the situations when the digital data, being sent over the high-speed parallel communication line, is a set of logical zeroes; each of the respective data output drivers is sinking current through its Vss pin to maintain the data-communication line at a logic low level and virtually no current is being drawn by each output driver""s Vdd pin. Assuming that the digital data being sent over the parallel communication line is suddenly switchecd from the set of logical zeroes to a set of logical ones, there would be a significant change (e.g., increase) in the current levels flowing between the internal Vdd and Vss pads and the respective Vdd and Vss nodes of each output driver. The Vdd will increase in current flow and the Vss will decrease in current flow.
This data-dependent current change causes large current fluctuations at the internal Vdd and Vss pads which, in turn, result in significant voltage drops across the series resistance and inductance inherent in the lines feeding the internal Vdd and Vss pads. Because the output drivers cannot suddenly change from a logical zero to a logical one until the voltage at the Vdd and Vss nodes of the output drivers recovers, there can be significant delays before the transmitted data signals fully reach the minimum voltage levels necessary to characterize the signals as logical ones. Consequently, such communication results in signal transmission delays, or skew between the signals and the receive clocks. In the higher-speed applications, this skew effect can be a significant percentage of the clock frequency; therefore the likelihood of data degradation increases. With advancements requiring further reductions in the power supply levels and further increases in clock rates, this skewing problem becomes more pronounced.
For high-speed data-transmission applications, there are various other disadvantages. For example, many interfaces are designed without sufficient consideration of the space and material costs in the number of power nodes and conductors required for passing such high-speed data signals over the parallel busses. By reducing the rate of current consumption for this high-speed communication, the number of power nodes and conductor pins can be reduced; in a power-critical application, such reductions can be significant. Moreover, reducing the current flow in high-speed parallel data communication applications can substantially reduce electromagnetic interference (xe2x80x9cEMIxe2x80x9d) which, in turn, can reduce the likelihood of signal recovery problems at the receiving module and thereby reduce the need for expensive and often burdensome EMI shielding.
Accordingly, improving data communication over parallel busses permits more practicable and higher-speed parallel bussing applications which, in turn, can directly lead to higher-powered, higher-functioning circuits that preserve data integrity and are sensitive to needs for reducing implementation space and power consumption.
Various aspects of the present invention are directed to data transfer over parallel-communication line circuits in a manner that addresses and overcomes the above-mentioned issues and can be used in conjunction with the embodiments disclosed in the above-mentioned patent documents. In one application involving a high-speed data transfer over a parallel data circuit, an example embodiment of the present invention permits significant increases in the data-transmission rate while maintaining data integrity. In certain embodiments, the present invention reduces current flow between transmitting and receiving modules and thereby causes a reduction in EMI, reduces the number of power pins (or, more generally, power nodes) required for the parallel data, and/or reduces the I/O delay and the skew from voltage sag in the signals passed over the parallel data interconnect.
One particular example embodiment involves a data communication arrangement in which digital data is transferred in parallel. The arrangement includes a communication channel and an interface circuit. The communication channel is adapted to transfer the digital data, and the interface circuit is coupled to the communication channel and adapted to process a set of X bits of the digital data. Each set of X bits is converted to a unique set of encoded Y bits, where Y is greater than X, with the encoding designed to increase the balance between the number of ones and the number of zeroes in the set of Y bits. By increasing this balance, the overall power consumption by the parallel-bit drivers remains relatively constant and skew, otherwise caused by fluctuations in the voltage rails at the drivers, is largely mitigated.
According to a method implementation, the present invention is directed to a method for passing digital data between first and second nodes interconnected via a parallel communication channel. The parallel communication channel and a clock communication path are adapted to transfer the digital data at the data-transmission rate. A parallel data circuit is adapted to process (e.g., read, write and/or interpret) a set of X bits of the digital data. The set of X bits is encoded into a set of Y bits, where Y is greater than X and to increase the exact balance between the number of ones and the number of zeroes in the set of Y bits.
According to another example embodiment of the present invention, the set of X data bits is encoded so that there is a balanced number of ones and zeroes in each set of Y data bits.
Other example embodiments of the present invention are respectively directed to the encoding, decoding and system-processing aspects of such interfaces.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description that follow more particularly exemplify these embodiments.